Inline and &#34;Y&#34; input-output bus topology

ABSTRACT

Various bus trace topologies are provided which allow for shorter stub lengths, reduced motherboard costs, more efficient routing between multiple agents, and bus traces with better matched characteristic impedances.

FIELD

[0001] The present invention is directed to circuit boards, and moreparticularly, bus topologies for circuit boards.

BACKGROUND

[0002] With increasing processor clock rates in the personal computer,workstation, and server industry, there is a pressing need to providehigh speed, economical bus topologies. In particular, designing for highspeed and economical communication among more than one processor oragent connected to a bus presents various challenges.

[0003] Over the years, many bus topologies have been designed. Forexample, FIG. 1 illustrates a “3D” topology (e.g., vertical cards on amotherboard give the interconnect a 3D nature) in which processormodules 102, along with their associated heat sinks 104, are mounted onprocessor cards 106, which are connected together to chip set 108 viabus 109 on motherboard 110. (In an actual embodiment, bus 109 and othertraces indicated in FIG. 1 may not be visible.) The connections betweenan agent, such as a microprocessor, and a bus are often referred to asstubs, and are indicated by numeral 112 in FIG. 1. For someapplications, the stub lengths for the 3D topology of FIG. 1 are toolong, resulting in undesirable signal reflections.

[0004] Yet another bus topology is illustrated in FIG. 2, sometimescalled a “2.5D”topology (because there is less vertical dimension whencompared to the 3D topology of FIG. 1). For this topology, components(processors or agents) 202, along with their associated heat sinks 204,are mounted on both sides of motherboard 206, facing each other, usingconnectors 210, and are connected to chip set 208 via bus 209. A stub isidentified by numeral 212, but not all stubs are shown. Such topologiesare relatively expensive due to motherboard assembly costs. Also, forthe topology of FIG. 2, some of the stubs may be too close to eachother, so that signal reflections pose a more serious problem.

[0005] Busses with many traces may also present design challenges. Someprior art bus topologies use many layers in the motherboard to route thebus traces to chip packages. However, this adds to motherboardcomplexity and cost. Alternatively, some prior art bus topologies routethe bus traces on only one layer or a few layers of the motherboard. Butbecause the dimension of the chip package is often smaller than thephysical width occupied by the bus traces when deposited on one layer,some of the stubs may be too long for some applications.

[0006] Embodiments of the present invention are directed to addressingthese problems.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007]FIG. 1 illustrates a prior art bus topology.

[0008]FIG. 2 illustrates another prior art bus topology.

[0009]FIG. 3 provides an edge view of an embodiment of the presentinvention.

[0010]FIGS. 4a and b provide two plan views illustrating an embodimentof the present invention having an inline topology.

[0011]FIGS. 5a and b provide edge and top views, respectively, of anembodiment of the present invention having a “Y” topology.

[0012]FIG. 6 provides a plan view of a bus trace positioned above aconductive plane with de-gassing holes according to an embodiment of thepresent invention.

[0013]FIG. 7 provides a plan view of another embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0014]FIG. 3 provides an edge view of an embodiment of the presentinvention. Mounted on one side of motherboard (substrate) 302 are agents304, such as, for example, microprocessors. These agents communicate viabus 306 and stubs 308 with chip set 310. For simplicity, only one tracefor bus 306 is shown, and only one stub is shown for each agent. Inpractice, bus 306 will comprise several or more traces, and each agentmay be connected to bus 306 via many stubs. (Bus 306 may not be visiblefrom an edge view of an actual embodiment.) In the particular embodimentof FIG. 3, agents 304 are mounted on connectors 310 and aresubstantially colinear in their placement upon the motherboard. Agents304 are mounted with their faces substantially parallel to the face ofmotherboard 302. In this way, stubs 308 are kept relatively small inlength.

[0015]FIGS. 4a and 4b provide additional views of the embodiment of FIG.3. FIG. 4a provides a top pictorial view of agent 406 comprising die 402and package 404, where the arrow indicates the general bus directionwith respect to the orientation of die 402 and package 404. As seen fromFIG. 4a, the direction of the bus lines is substantially parallel to theedge of package 404. Also, die I/O pads 418 should be near the peripheryof die 402 so that they are close to package pins 420 so as to shortenstub lengths and to allow an easier escape pattern.

[0016]FIG. 4b provides a plan view of vias 408 for agent 406 withrespect to a direction perpendicular to motherboard 302. For simplicity,agent 406 is not shown in FIG. 4b, and only three stubs are explicitlyshown. In practice, many or all of vias 408 may be connected to stubs.In the example of FIG. 4b, four bus traces or lines 410, 412, 414, and416 are routed with respect to the via orientation as shown. In FIG. 4b,bus traces 410, 412, 414, and 416, and vias 408, may not necessarily liein the same plane.

[0017] In general, for the embodiment of FIG. 4b and other embodiments,vias 408 define a regular array. The region between two consecutive rows(or columns) of a regular array of vias define a channel. For theembodiment of FIG. 4b and other embodiments, bus lines are routed so asto be within or underneath one and only one channel. That is, in an areaor region of a board directly underneath a agent that is to be connectedto a bus, individual bus traces making up the bus do not cross from onechannel to the next. For the particular embodiment shown in FIG. 4b, bustraces 410 and 412 are in one channel, and bus traces 414 and 416 are inanother channel. Bus topologies such as those according to theembodiments of FIGS. 3, 4a, and 4 b allow for relatively small stublengths, and are found to address some or all of the problems cited inthe Background.

[0018] For some applications, the length of the bus lines may introducerelatively large latencies. In such cases, for some embodiments, sourcesynchronous communication may be employed, where the source (bus driver)sends both data and clock signals. In some embodiments, a quad pumpedbus protocol may be used, where the ratio of the source synchronousclock rate to a common clock rate is equal to four, for example.

[0019] An embodiment for wide busses is illustrated in FIGS. 5a and 5 b.FIG. 5a provides an edge view of a motherboard 512 having interconnector514 mounted on it. Chip package 516 is mounted on interconnector 514.Interconnector 514 provides a connection between chip package 516 andbus traces (not shown in FIG. 5a) on motherboard 512, where the bustraces occupy a wider width than the dimension of chip package 516. Aplan view from the top of chip package 516 is shown in FIG. 5a, wherefor simplicity only one bus trace 518 is shown. (Parts of bus trace 518may not be visible in an actual embodiment.)

[0020] In FIG. 5b, bus trace 518 connects with interconnector 514 by wayof vias 502 and 504. Bus trace 518 also extends on interconnector 514,shown in FIG. 5b, as portions 506 and 508. This extension of bus trace518 on interconnector 514 connects with chip package 516 by way of via509, and stub 510 provides the connection to die 520. In someembodiments, bus trace portions 506 and 508 may be linear, whereas inothers they may be curved or non-linear, or any combination thereof. Inone embodiment, the composition of interconnector 514 is such that thecharacteristic impedance of the portions 506 and 508 of bus trace 518 oninterconnector 514 is substantially equal to the characteristicimpedance of bus trace 518 on motherboard 512 so as to reduce signalreflection.

[0021] For the embodiment of FIGS. 5a and 5 b, the stub lengths arerelatively short due to the use of interconnector 514. This reducessignal degradation due to signal reflection. In the particularembodiment of FIGS. 5a and 5 b, interconnector 514 is on the same sideof motherboard 512 as chip package 516, so that interconnector 514 maybe termed an interposer. However, in other embodiments, interconnector514 may be on the opposite side of motherboard 512 relative to chippackage 516, so that in these embodiments interconnector 514 may betermed an underposer.

[0022] Some busses comprise one or more traces and a conductive plane,so that a trace and the conductive plane comprise a structure for guidedelectromagnetic wave propagation, i.e., a transmission line. Thecharacteristic impedance of a transmission line may be effected bydiscontinuities in the conductive plane and surrounding dielectricmaterial.

[0023] In particular, de-gassing holes are introduced into a conductiveplane to allow for gasses to escape, especially during manufacturing.These de-gassing holes present discontinuities in the conductive plane.Often, these de-gassing holes are aligned with each other to form asubstantially regular array of holes, but this is not always necessarilythe case. FIG. 6 provides a simplified plan view of bus traces 601 and602 above conductive plane 604 having de-gassing holes 606.

[0024] In the embodiment of FIG. 6, bus traces 601 and 602 are alignedwith respect to de-gassing holes 606 such that their characteristicimpedances are substantially equal to each other. This may beaccomplished by arranging traces 601 and 602 so that they have similarenvironments. For example, traces 601 and 602 may be routed so that eachtrace passes over the same local average of holes per unit length. Thislocal average may be taken over a quarter-wavelength λ/4. Preferably,the sizing of de-gassing holes 606 are such that they are substantiallysmaller than the wavelength λ of the electromagnetic wave to bepropagated by traces 601 and 602. For example, the diameter of thedegassing holes may be less than λ/10.

[0025] For the embodiment of FIG. 6, it is also preferable thatvariations in the characteristic impedance along the length of a traceare minimized. One approach is to route a trace so that the localaverage of holes per unit length passed by the trace is substantiallyindependent of position along the trace.

[0026]FIG. 7 illustrates another embodiment in which there are two pinfields, denoted by 720 and 722, for two agents (not shown). Three traces702, 704, and 706 are routed on a circuit board (not shown) and areconnected, respectively, to vias 708, 710, and 712 in pin field 720. Inmany prior art routing techniques, only two traces per channel arerouted because each trace may easily connect with vias defining thechannel, and thus the embodiment of FIG. 7 represents an improvementover such prior art routing techniques. Note that vias 708, 710, and 712lie within one row of vias. Traces 702, 704, and 706 are also routed tosecond pin field 722 and connect with vias 714, 716, and 718, which alsolie within one row of vias.

[0027] The row of vias containing via 724 and the row of vias containingvia 712 define a first channel in pin field 720, and the row of viascontaining via 712 and the row of vias containing via 726 define asecond channel in pin field 720. As seen in FIG. 7, the traces enter onechannel and exit an adjacent channel so that connections to the vias donot need to overlap the other traces. Routing multiple traces perchannel reduces printed circuit board costs.

[0028] The embodiment of FIG. 7 may be extended to other embodimentswith more than three traces in which vias within one row are to beconnected to the traces. Furthermore, the connected vias need not beadjacent to one another. Also, there may be other layers in the circuitboard in which other traces are deposited and routed so that tracesenter one channel and exit and adjacent channel.

[0029] Various modifications may be made to the disclosed embodimentswithout departing from the scope of the invention as claimed below.

What is claimed is:
 1. A circuit board having two sides, the circuitboard comprising: a substrate having a first array of vias to connect toa first agent, the first array of vias defining a first set of channelson the substrate, and having a second array of vias to connect to asecond agent, the second array of vias defining a second set of channelson the substrate; and a bus comprising bus traces, wherein each bustrace is routed in only one channel belonging to the first set ofchannels and routed in only one channel belonging to the second set ofchannels.
 2. The circuit board as set forth in claim 1 , wherein thefirst and second agents are mounted upon only one of the two sides ofthe circuit board.
 3. The circuit board as set forth in claim 1 ,wherein the bus propagates a source synchronous clock signal having asource synchronous clock frequency and a common clock signal having acommon clock frequency, wherein the source synchronous clock frequencyis at least twice the common clock frequency.
 4. The circuit board asset forth in claim 3 , wherein the first and second agents are mountedupon only one of the two sides of the circuit board.
 5. The circuitboard as set forth in claim 1 , wherein the first array of vias arearranged in substantially linear rows and the second array of vias arearranged in substantially linear rows.
 6. An electronic systemcomprising: a circuit board having a first trace segment and a secondtrace segment; and an interconnector supported by the circuit board, theinterconnector having a third trace segment connected to the first tracesegment by way of a first via, and having a fourth trace segmentconnected to the second trace segment by way of a second via.
 7. Theelectronic system as set forth in claim 6 , wherein first, second,third, and fourth trace segments have substantially equivalentcharacteristic impedances.
 8. The electronic system as set forth inclaim 6 , further comprising: a die; and a die package to support thedie, the die package having a stub connected to the third and fourthtrace segments by way of a third via, wherein the first, second, third,and fourth trace segments form a bus trace.
 9. A circuit boardcomprising: a conductive plane having de-gassing holes; a first bustrace substantially parallel to the conductive plane; a second bus tracesubstantially parallel to the conductive plane; and a dielectricdisposed between the conductive plane and the first and second bustraces, the combination of the first and second bus traces with theconductive plane and dielectric having, respectively, first and secondcharacteristic impedances and to guide electromagnetic radiation havinga wavelength, wherein the de-gassing holes are substantially smallerthan the wavelength, and wherein the first and second bus traces arepositioned relative to the de-gassing holes so that the first and secondcharacteristic impedances are substantially equal to each other.
 10. Thecircuit board as set forth in claim 9 , wherein the de-gassing holeshave diameters less than one-tenth of the wavelength.
 11. A circuitboard comprising: a conductive plane having de-gassing holes; a firstbus trace substantially parallel to the conductive plane; a second bustrace substantially parallel to the conductive plane; and a dielectricdisposed between the conductive plane and the first and second bustraces, the combination of the first and second bus traces with theconductive plane and dielectric to guide electromagnetic radiationhaving a wavelength, wherein the de-gassing holes are substantiallysmaller than the wavelength, wherein the first bus trace passes over afirst local average of de-gassing holes per unit length, wherein thesecond bus trace passes over a second local average of de-gassing holesper unit length, and wherein the first and second bus traces arepositioned relative to the de-gassing holes so that the first and secondlocal averages of de-gassing holes per unit length are substantiallyequal to each other.
 12. The circuit board as set forth in claim 11 ,wherein the second and first local averages are taken over one quarterof the wavelength.
 13. The circuit board as set forth in claim 11 ,wherein the de-gassing holes have diameters less than one-tenth of thewavelength.
 14. A circuit board comprising: a substrate having an arrayof vias, the array of vias defining a set of channels on the substrate;and three bus traces routed on the circuit board so as to enter a firstchannel belonging to the set of channels and to exit a second channelbelonging to the set of channels, the first and second channels adjacentto each other so that there is one row of vias between the first andsecond channels, wherein each of the three bus traces are connected to avia belonging to the row of vias so as to define three connections,wherein the three connections do not overlap the three bus traces.